The present invention is directed to a flip-flop circuit that cannot glitch or enter a metastable hang-up state due to asynchronous inputs. Digital logic circuits of the type used in computer systems have been faced with the problem that asynchronous signal inputs are sometimes necessary and unavoidable. A fault can occur when these asynchronous signal inputs (or a logical combination of these inputs) are used to stimulate a conventional memory element such as a latch or a flip-flop. Asynchronous signals into these types of devices have a finite probability of placing the device into a metastable state for an undefined period of time. This basic difficulty comes from the fact that any circuit or known circuit component that has memory in it, such as a flip-flop, may not settle into one of the two stable states (0 and 1) for an indefinite period following the operation under conflict. A conflict is defined as the situation that exists when one signal tries to set a flip-flop in one direction and, at the same time, another signal tries to set the flip-flop in the other direction. A flip-flop, considered as an ideal device, is always in either state 0 or state 1 at any given time, but a physically implemented flip-flop may, when operated in conflict, get into a metastable state which is neither 0 nor 1 and the flip-flop may remain in this state for an indefinite length of time. The length of time for which a metastable state lasts is random and is best characterized by probability. The probability that a conventional memory element will enter a metastable state is directly dependent on the likelihood of simultaneous activation of two or more signal inputs. Also the affect of a metastable state may vary from a "don't care" condition in some circuits to a complete system failure in others. An arbitration circuit to determine priorities for a shared computer bus is particularly sensitive to the metastable problem due to the chance and frequency of simultaneous inputs being relatively high and the consequence of a metastable condition being usually severe. A number of prior art devices have attempted to minimize and/or eliminate this particular problem. One particular prior art device is disclosed in U.S. Pat. No. 3,219,845, entitled "Bistable Electrical Circuit Utilizing NOR Circuits Without AC Coupling", by N. Y. Nieh. The circuit of the referenced patent is comprised of four logic gates which are connected to operate as a JK flip-flop having a reset and a set input. Feedback is provided from two of the logic elements back to the inputs of the preceding logic elements. Inserted in each of the feedback paths is a delay means comprised of shunt capacitance. The delay means produces a delay in transferring pulses between the stages of the circuit. This delay prevents a signal race condition from existing.
Another circuit of interest is described in U.S. Pat. No. 3,824,409, entitled "Arbiter Circuits", S. S. Patil. The circuit of the referenced patent uses a first arbiter circuit having a narrow acceptance window through which signals may pass as long as the difference between the arrival of the signals is within the time slot of the window. If two or more signals arrive at times that are greater than the time slot of the window, the first signal to arrive is received and transmitted while all others are stopped. In order to then determine which of the two signals that has passed through the first arbiter circuit is in reality first in time, a delay element is inserted into the signal path of one of the passed signals. This, in turn, increases the time separation between the two signals which are again passed through an arbiter circuit, which circuit has its window fixed in duration so as to stop the second signal. The signals passing through the arbiter circuit can then be applied to latching circuits or flip-flop circuits with a minimum probability of conflict.
The circuit of the present invention is designed to completely eliminate the probability of a glitch or a metastable state with a minimum use of elements.